Job Description

As an ASIC Auto Place and Route Technology Development Engineer you will be responsible for, but not limited to the following:

• Development of ASIC Auto Place and Route design flows (including 3DIC Flows) and collateral using Synopsys Fusion Compiler and/or Cadence Innovus.

• Perform detailed evaluation of tool run results to validate proper tool behavior and identify root cause for any discrepancies found.

• Develop and enhance automation scripts for tool regression and quality.

• Generation and quality checking of APR tech files and other required tool collaterals.

• Develop and enhance automation scripts for collateral generation and quality.

• Develop and test Engineering Design Automation EDA tools and create flow scripts to analyze and test design methodologies.

• Designing, deploying and testing efficiency of tools in achieving design goals and collaborating with design teams on methodology development.

• Candidate should be willing to apply design methodologies to help execute projects effectively and successfully with high quality.

This is an entry level position and compensation will be given accordingly.

#Designdevelopment

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.

Knowledge and/or experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.

Minimum Qualifications:

Candidate must possess a bachelor’s with 3+ months experience or a master’s degree with 6+ months of experience in Electrical Engineering or Computer Engineering or related field.

3+ months experience in the following:

• Scripting knowledge.

Preferred Qualifications:

3+ months experience in the following:

-Knowledge of ASIC Design Flows

• Knowledge of ASIC design using Auto Place and Route (APR)

• Tcl programming

• Knowledge of Perl, Python or Ruby.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Other Locations

US, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

Annual Salary Range for jobs which could be performed in US, California: $91,500.00-$137,436.00

*Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.